Keysight provides a design-to-test workflow

In the face of increasing data center bandwidth, expectations for high-performance computing and server performance are driving the demand for high-density memory, superfast speeds, or Memory. Dynamic RAM (DRAM) DDR5.

Keysight provides workflow from design to test - photo 1

Keysight’s PathWave ADS 2023 solution for high-speed digital design contains improvements in Memory Designer for DDR5 emulation

Operating at twice the data rate of DDR4 reduces design margins, making it difficult for hardware designers to optimize printed circuit boards (PCBs) to minimize reflection effects , crosstalk and jitter. In addition, the low voltage, high current, and new equalization requirements in DRAM receivers create new, difficult and costly, signal integrity challenges.

Keysight’s PathWave ADS 2023 solution for high-speed digital design ensures rapid setup of simulations and advanced measurements, and provides designers with critical information to address challenges. about data integrity.


The solution’s Memory Designer feature quickly creates parametric memory axes with pre-layout builder simulation, allowing designers to explore trade-in options in the system, reducing design time Design and reduce product development risk for DDR5 memory systems, low-power dual-speed memory, Low-Power Double Data Rate (LPDDR5/5x) and graphics dual-speed memory Graphics Double Data Rate ( GDDR6/7).

Stephen Slater, PathWave HSD Product Management Manager at Keysight Technologies, said: “Keysight has always been at the forefront of test and channel emulation technology within memory industry standards organizations, including JEDEC We are committed to developing the widest range of DDR-enabled products and services, including the full design-to-test workflow for DDR5 memory, from simulation, to test and repair ( probing and fixturing)”.

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